Each memory for constituting a DRAM (Dynamic Random Access Memory) is generally provided with an N-channel transistor (N-transistor) 100 and a capacitor 101, as shown in FIG. 9.
A drain of the N-transistor 100 is connected to a bit line BL, a gate thereof is connected to a word line WL and a source thereof is connected to a node N100. Further, a substrate bias voltage Vbb (e.g. −1.0V) which is outputted from a charge pump circuit (not shown) is applied to a back gate of the N-transistor 100.
The capacitor 101 is formed, e.g. as a parallel flat plate type. One terminal of the capacitor 101 is connected to the node N100 while the other terminal thereof is connected to a node N101. A voltage which is half as much as a first power supply voltage Vcc is applied to the node N101.
FIG. 10 shows a sectional view of each memory cell. An N-type well 111 is formed on a P-type substrate 110 and a P-type well 112 is formed inside the N-type well 111. Further, an N+ type impurity region 121 and an N+ type impurity region 122 are formed inside the P-type well 112, which respectively form a source and a drain of the N-transistor 100.
A second power supply voltage Vss (e.g. 0V) is applied to the P-type substrate 110 and the first power supply voltage Vcc is applied to the N-type well 111 while the substrate bias voltage Vbb is applied to the P-type well 112.
Since the substrate bias voltage Vbb is applied to the P-type well 112, even if there is a noise on the word line WL, an electric charge which is charged in the capacitor 101 is not moved toward the N+ type impurity region 122 through the N+ type impurity region 121. That is, it is possible to prevent data stored in each memory from leaking.